[PYTHON] I started PYNQ (2) -Overlay self-made-

Introduction

The usage of the existing Overlay seems to have been introduced in other articles, so skip it and proceed to the next. So, this time, I will make my own overlay as a continuation of previous. This video ~~ Paku ~~ Refer to it and make an overlay of c = a + b.

What is Overlay

The logic circuit part of PYNQ-Z1 can be handled from a program as if it were a library (?). For details, go to Official.

Execution environment

--Development PC: Windows10 - Vivado Design Suite - HLx Edition - 2019.2

The download alone will be 10GB, and after completion it will be close to 50GB, so you should work on it with sufficient time and storage. This time, I used Webpack (free version).

• PYNQ-Z1

procedure

Here, let's try a circuit that just does c = a + b according to the tutorial.

Adder implementation

First, prepare a circuit that only adds on the FPGA.

1. 1. Launch a new project

1. Start Vivado HLS.
2. In Project Configuration, specify project name as adder and Location as appropriate. (** If Japanese is included in the path, an error may occur later **)
3. In ʻAdd Remove Files (1st)`, enter add in TopFunction to create NewFile-> adder.cpp
4. Ignore the second ʻAdd Remove Files` and proceed
5. When you reach Solution Configuration, search and select Part Selection-> xc7z020clg400-1.
6. Press Finish to create a project

2. Implementation

Once a new project is created, it will be implemented.

1. 1. Double-click Source-> adder.cpp from the Explorer tab on the left side of the screen
2. Enter the following Code (https://pynq.readthedocs.io/en/v2.1/overlay_design_methodology/overlay_tutorial.html)

adder.cpp

void add(int a, int b, int& c) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE s_axilite port=a
#pragma HLS INTERFACE s_axilite port=b
#pragma HLS INTERFACE s_axilite port=c

    c = a + b;
}

3. 3. Execute

Press the green arrow in the upper left of the image below. If all goes well, you should see a screen like this.

Four. Take a look at the address

The following files are generated in solution-> impl-> misc-> drivers-> add_v1_0-> src-> xadd_hw.h on the Explorer tab. If you look at this, you can see the correspondence table between variables and addresses.

Five. Export

This is to the right of the green arrow earlier and press ʻOK`.

Overlay implementation

Configure Overlay using the ʻadder` created earlier

0. Addition of PYNQ-Z1

Since the information of PYNQ-Z1 is not registered in the Vivado web pack, download the data from here. I used it. Expand this and copy it to C: \ Xilinx \ Vivado \ 2019.2 \ data \ boards \ board_files etc.

1. 1. Project creation

1. Launch Vivado
2. Select Create Project
3. When Create a New Vivado Project is displayed, click Next.
4. This time, set Project name to project_1 and select an appropriate folder for Location.
5. Select RTL Project for Project Type.
6. Select Default Part-> Board-> PYNQ-Z1.
7. When New Project Summary is displayed, create a project with Finish.

2. Create

We will continue to work with Vivado.

1. Select ʻIP INTEGRATOR-> Create Block Design` on the left side of the screen and press OK in the pop-up.
2. Click + and select Search-> ZYNQ7 Processing System
3. Run Block Automation -> OK
4. From Tools on the screen, go to Setting-> ʻIP-> Repository, press +, and select / add the ʻadder folder you created earlier.
5. Return to the original screen and add ʻadd this time. Also, change the name from ʻadd_0 to scalar_add.
6. Press Run Connection Automation.
7. Save (Ctrl + S) and right-click on Sources-> design_1-> Create HDL Wrapper-> ʻOK`
8. From the navigation on the left side of the screen, go to PROGRAM AND DEBUG-> Generate Bitstream-> Yes-> ʻOK`.
9. File -> Export -> Export Block Design -> OK

Overlay transfer

Now that you have created a set of files, copy them to PYNQ-Z1 and execute them.

File preparation

Copy the following 2 files in the project folder.

• project_1\project_1.runs\impl_1\design_1_wrapper.bit
• \project_1\project_1.srcs\sources_1\bd\design_1\hw_handoff\design_1.hwh
• project_1\design_1.tcl

Rename them to ʻadder.bit, ʻadder.hwh, and ʻadder.tcl` for easy understanding.

Connect to PYNQ

Enter \\ pynq in the URL part of Explorer to tamper with the internal folder. Both ID and password are xilinx.

File placement

Create a new directory ʻadderinNetwork / pynq / xilinx / pynq / overlay and copy ʻadder.bit, ʻadder.hwh, ʻadder.tcl.

Try using Overlay from Python

Preparing jupyter

Access [http: // pynq: 9090](http: // pynq: 9090) and log in to jupyter (ID / password is xilinx). After connecting, create a new Python3 note from New on the home screen and open it.

Try out

Then follow the Official.

First read.

In[1]

from pynq import Overlay

overlay = Overlay('/home/xilinx/pynq/overlays/adder/adder.bit')

In the next two, each usage is displayed in text.

In[2]

overlay?

In[3]

add_ip = overlay.add_0
add_ip?

Let's calculate 4 + 5.

In[4]

add_ip.write(0x10, 4)
add_ip.write(0x18, 5)
add_ip.read(0x20)    #Is output as 9

This is the same.

In[5]

add_ip.register_map.a = 3
add_ip.register_map.b = 4
add_ip.register_map.c

Finally

It worked for the time being. Next time, I would like to do something like speeding up arrays by parallel processing.