Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Practice)

Introduction

The author provides Debian GNU / Linux for Ultra96 / Ultra96-V2 (ZynqMP) 1. In addition, XRT (Xilinx Runtime) is an environment for running programs developed in the development environment (Vitis) provided by Xilinx on the platform 2.

Originally, XRT for MPSoC Edge Device works only in the Linux environment (Petalinux) provided by Xilinx, but the procedure for running XRT on Debian GNU / Linux for Ultra96 / Ultra96-V2 is included in some parts. I will explain them separately.

This article describes the steps to run a sample program on Debian GNU / Linux for Ultra96 / Ultra96-V2 running XRT.

Caution

__ The Debian Package presented in this article is not official by Xilinx. __

Sample introduction

The XRT sample presented in this hands-on version was provided by @ marsee101, who writes the blog ["FPGA Room"]. We would like to take this opportunity to thank you. See the next page of the blog for how to build this sample and detailed instructions.

Download sample

The sample binary files introduced above are available on github with the permission of @ marsee101.

Download this repository to Ultra96-V2 with ZynqMP-FPGA-XRT installed.

shell$ git clone https://github.com/ikwzm/ZynqMP-FPGA-XRT-Example-1-Ultra96
Cloning into 'ZynqMP-FPGA-XRT-Example-1-Ultra96'...
remote: Enumerating objects: 13, done.
remote: Counting objects: 100% (13/13), done.
remote: Compressing objects: 100% (10/10), done.
remote: Total 13 (delta 3), reused 13 (delta 3), pack-reused 0
Unpacking objects: 100% (13/13), done.
shell$ cd ZynqMP-FPGA-XRT-Example-1-Ultra96

XRT environment settings

Set environment variables for XRT. XRT provides /opt/xilinx/xrt/setup.sh for setting environment variables, so use this.

shell$ source /opt/xilinx/xrt/setup.sh
XILINX_XRT      : /opt/xilinx/xrt
PATH            : /opt/xilinx/xrt/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games
LD_LIBRARY_PATH : /opt/xilinx/xrt/lib:
PYTHONPATH     : /opt/xilinx/xrt/python:

FPGA bitstream file preparation

The downloaded repository already contains an FPGA bitstream file (streaming_lap_filter5.bin), but this section describes how to create this bitstream file.

This bitstream file is the basis for Partial Reconfiguration (see "Preparing the Device Tree" in the Installation section for more information). Originally, the base bitstream file should be created separately when xclbin was created, but in this sample example, it is the same as the bitstream file contained in the "accidentally" xclbin file. Therefore, first retrieve the bitstream file using the xclbinutil command.

shell$ xclbinutil --input streaming_lap_filter5.xclbin --dump-section BITSTREAM:RAW:streaming_lap_filter5.bit
XRT Build Version: 2.6.0 (2019.2_Ultra96)
       Build Date: 2020-03-26 13:46:25
          Hash ID: 4a669990dd872f3b683009c0e2200b3bd3d2a9c0
------------------------------------------------------------------------------
Warning: The option '--output' has not been specified. All operations will
         be done in memory with the exception of the '--dump-section' command.
------------------------------------------------------------------------------
Reading xclbin file into memory.  File: streaming_lap_filter5.xclbin
Section: 'BITSTREAM'(0) was successfully written.
Format: RAW
File  : 'streaming_lap_filter5.bit'
Leaving xclbinutil.

Then use the bootgen command to create streaming_lap_filter5.bin. streaming_lap_filter5.bif is included in the repository.

shell$ bootgen -arch zynqmp -image streaming_lap_filter5.bif -o tmp.bin
****** Xilinx Bootgen v2019.2
  **** Build date : Jan 16 2020-08:00:00
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

The bootgen command is not included in the XRT (Xilinx Runtime). Please install by referring to the following article.

Preparation of zocl

When you installed ZynqMP-FPGA-XRT, zocl (Linux kernel module for MPSoC Edge Device) was also installed. However, zocl is not enabled just by installing it on Linux. A Device Tree is required to enable zocl. Therefore, the following Device Tree is prepared.

zocl.dts


/dts-v1/; /plugin/;
/ {
	[email protected] {
		target-path = "/fpga-full";
		__overlay__ {
			firmware-name = "streaming_lap_filter5.bin";
		};
	};
	[email protected] {
		target-path = "/[email protected]";
		__overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			zyxclmm_drm {
				compatible = "xlnx,zocl";
				status = "okay";
				reg = <0x0 0xA0000000 0x0 0x10000>;
			};
			fclk0 {
				compatible    = "ikwzm,fclkcfg-0.10.a";
				clocks        = <&zynqmp_clk 0x47>;
				insert-rate   = "100000000";
				insert-enable = <1>;
				remove-rate   = "1000000";
				remove-enable = <0>;
			};
		};
	};
};

Copy streaming_lap_filter5.bin to / lib / firmware.

shell$ sudo cp streaming_lap_filter5.bin /lib/firmware/

Device Tree Overlay zocl.dts. We have prepared a ruby script for Device Tree Overlay called dtbicfg.rb, so use this.

shell$ sudo ./dtbocfg.rb --install zocl --dts zocl.dts
<stdin>:14.16-18.6: Warning (unit_address_vs_reg): /[email protected]/__overlay__/zyxclmm_drm: node has a reg or ranges property, but no unit name

Check the kernel log with dmesg. It is successful if you can see that streaming_lap_filter5.bin was programmed into the FPGA by the fpga manager, the zocl kernel module was loaded, and that fclkcfg set the frequency of PL Clock0 to 100MHz.

shell$ dmesg | tail -12
[ 4824.024388] fpga_manager fpga0: writing streaming_lap_filter5.bin to Xilinx ZynqMP FPGA Manager
[ 4824.176574] [drm] Probing for xlnx,zocl
[ 4824.176710] [drm] FPGA programming device pcap founded.
[ 4824.176715] [drm] PR Isolation addr 0x0
[ 4824.178392] [drm] Initialized zocl 2018.2.1 20180313 for a0000000.zyxclmm_drm on minor 1
[ 4824.180629] fclkcfg [email protected]:fclk0: driver installed.
[ 4824.180640] fclkcfg [email protected]:fclk0: device name    : [email protected]:fclk0
[ 4824.180644] fclkcfg [email protected]:fclk0: clock  name    : pl0_ref
[ 4824.180649] fclkcfg [email protected]:fclk0: clock  rate    : 99999999
[ 4824.180674] fclkcfg [email protected]:fclk0: clock  enabled : 1
[ 4824.180677] fclkcfg [email protected]:fclk0: remove rate    : 1000000
[ 4824.180681] fclkcfg [email protected]:fclk0: remove enable  : 0

Run the sample

Run the sample. If you get the following result, you are successful.

shell$ ./streaming_lap_filter5.exe streaming_lap_filter5.xclbin
Using FPGA binary file specfied through the command line: streaming_lap_filter5.xclbin
Found Platform
Platform Name: Xilinx
Loading: 'streaming_lap_filter5.xclbin'
total time = 0.001533 sec
Success HW and SW results match

reference

[Overview]: https://qiita.com/ikwzm/items/0d3a8adfe725cd17f932 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Overview) "@Qiita" [Build]: https://qiita.com/ikwzm/items/d8013ea91125a3fc46aa "Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Build)" @Qiita " [Installation]: https://qiita.com/ikwzm/items/6612eacc4a0d324a0a68 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Installation) "@Qiita" [Practice]: https://qiita.com/ikwzm/items/58cfea3f9d0f42840511 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Practice) "@Qiita" [Vitis Edition]: https://qiita.com/ikwzm/items/e70d8d0e44fe3784a708 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Vitis Edition) "@Qiita" ["Run bootgen on Debian GNU / Linux, Ubuntu" @Qiita]: https://qiita.com/ikwzm/items/97811fcff7876181209f "Run bootgen on Debian GNU / Linux, Ubuntu" @Qiita " ["FPGA Room"]: https://marsee101.blog.fc2.com "" FPGA Room "" ["Trying a storming connection using the RTL kernel in Vitis 2019.2 1"]: https://marsee101.blog.fc2.com/blog-entry-4823.html "" Storming using the RTL kernel in Vitis 2019.2 Try the connection 1 ”” ["Trying a storming connection using the RTL kernel in Vitis 2019.2 2"]: https://marsee101.blog.fc2.com/blog-entry-4824.html "" Storming using the RTL kernel in Vitis 2019.2 Try the connection 2 ”” ["Trying a storming connection using the RTL kernel in Vitis 2019.2 3"]: https://marsee101.blog.fc2.com/blog-entry-4825.html "" Storming using the RTL kernel in Vitis 2019.2 Try the connection 3 ”” ["Try storming connection using RTL kernel in Vitis 2019.2 4"]: https://marsee101.blog.fc2.com/blog-entry-4826.html "" Storming using RTL kernel in Vitis 2019.2 Try the connection 4 ””

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