Run XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Installation)

Introduction

The author provides Debian GNU / Linux for Ultra96 / Ultra96-V2 (ZynqMP) 1. In addition, XRT (Xilinx Runtime) is an environment for running programs developed in the development environment (Vitis) provided by Xilinx on the platform 2.

Originally, [XRT] for MPSoC Edge Device works only in the Linux environment (Petalinux) provided by Xilinx, but the procedure for running XRT on Debian GNU / Linux for Ultra96 / Ultra96-V2 is included in some parts. I will explain them separately.

This article describes the steps to install XRT on Debian GNU / Linux for Ultra96 / Ultra96-V2.

Caution

__ The Debian Package presented in this article is not official by Xilinx. __

Corresponding platform

At this time, we have confirmed that it can be installed only on the following platforms.

The Linux Kernel can be found at the following URL:

The distribution can be found at the following URL:

Please refer to each URL to install on Ultra96. Also, please refer to the following articles.

Obtaining the Debian Package

["Run XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Build)" @Qiita] Build the Debian Package of XRT by the method explained in (), or Debian at the following URL Download the Package.

Before installation

Please install the following packages before installing.

The package introduced above explicitly declares a dependency when building xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb.

In addition to the above, please install the following packages.

If this package is not installed, pip will try to install pyopencl during the installation of xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb. When installing pyopencl with pip, I had to compile a program written in C, which caused various troubles and eventually failed to install. It's better to have pyopencl pre-built for Debian / Ubuntu installed from the beginning to avoid trouble.

Installation of XRT (Xilinx Runtime) Package

Install xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb with the dpkg command. Note that when you install this package, you will use the dkms mechanism to build the zocl kernel module in the middle of the process. Therefore, it takes time to install.

[email protected]:~$ cd work/ZynqMP-FPGA-XRT
[email protected]:~/work/ZynqMP-FPGA-XRT$ sudo dpkg -i xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb
Selecting previously unselected package xrt.
(Reading database ... 114691 files and directories currently installed.)
Preparing to unpack xrt_202010.2.6.0_Ubuntu_18.04-arm64-xrt.deb ...
Unpacking xrt (2.6.0) ...
Setting up xrt (2.6.0) ...
Unloading old XRT Linux kernel modules
rmmod: ERROR: Module zocl is not currently loaded
Invoking DKMS common.postinst for xrt
debconf: unable to initialize frontend: Dialog
debconf: (Dialog frontend will not work on a dumb terminal, an emacs shell buffer, or without a controlling terminal.)
debconf: falling back to frontend: Readline
Loading new xrt-2.6.0 DKMS files...
Building for 4.19.0-xlnx-v2019.2-zynqmp-fpga
Building initial module for 4.19.0-xlnx-v2019.2-zynqmp-fpga
Done.
zocl:
Running module version sanity check.
 - Original module
   - No original module exists within this kernel
 - Installation
   - Installing to /lib/modules/4.19.0-xlnx-v2019.2-zynqmp-fpga/updates/dkms/
depmod...
DKMS: install completed.
Finished DKMS common.postinst
Loading new XRT Linux kernel modules
Skipping pyopencl installation...

While building the kernel module, do not interrupt it with Ctrl-C etc., but wait until it finishes.

Device Tree preparation

The Debian Package installed in the previous section contains the Linux kernel module zocl for the XRT MPSoC Edge Device. However, zocl does not take effect just by installing it on Linux. A Device Tree is required to enable zocl.

ZynqMP-FPGA-Linux supports Device Tree Overlay. Device Tree Overlay actively adds and removes FPGA programs and kernel modules running Linux. zocl is also enabled using Device Tree Overlay.

The following is an example of Device Tree Overlay to enable zocl.

zocl.dts


/dts-v1/; /plugin/;
/ {
        [email protected] {
                target-path = "/fpga-full";
                __overlay__ {
                        firmware-name = "streaming_lap_filter5.bin";
                };
        };
        [email protected] {
                target-path = "/[email protected]";
                __overlay__ {
                        #address-cells = <2>;
                        #size-cells = <2>;
                        zyxclmm_drm {
                                compatible = "xlnx,zocl";
                                status = "okay";
                                reg = <0x0 0xA0000000 0x0 0x10000>;
                        };
                       fclk0 {
                                compatible    = "ikwzm,fclkcfg-0.10.a";
                                clocks        = <&zynqmp_clk 0x47>;
                                insert-rate   = "100000000";
                                insert-enable = <1>;
                                remove-rate   = "1000000";
                                remove-enable = <0>;
                        };
                };
        };
};

In this example, the zyxclmm_drm node shows the device tree for zocl.

In addition, there are two more important points about this Device Tree. The first is that fclk0 sets PL Clock 0 to 100MHz.

The second is that the firmware-name property is added to the fpga-full node to specify the bitstream file. This will cause the specified bitstream file to be programmed into the FPGA when the Device Tree is overlaid [3].

The bitstream contained in the xclbin file built by the Xilinx software development environment Vitis is actually for Partial Reconfiguration.

Partial Reconfiguration is a technology that dynamically rewrites only the specified area while it is originally programmed and operating on the FPGA. That is, the underlying bitstream file must be programmed into the FPGA before Partial Reconfiguration. Also, during Partial Reconfiguration, unlike a normal FPGA program, the entire FPGA is not reset.

When programming the xclbin file on the FPGA, zocl programs in Partial Reconfiguration mode. Therefore, the underlying bitstream file must be programmed into the FPGA before the zocl driver can be enabled.

Added on June 17, 2020

In the original article, "# size-cells = <1>;" "reg = <0x0 0xA0000000 0x10000>;", but with Linux Kernel 5.4 I get an error. Since Linux Kernel 5.4, it seems that it is no longer possible to set the value of "# size-cells" to a value different from the base Device Tree.

reference

[3]: https://qiita.com/ikwzm/items/2ff7d5429da8ace7c0bd "" FPGA support situation in Linux Kernel 4.10 "@Qiita" [ZynqMP-FPGA-Linux]: https://github.com/ikwzm/ZynqMP-FPGA-Linux "https://github.com/ikwzm/ZynqMP-FPGA-Linux" [XRT]: https://github.com/Xilinx/XRT "https://github.com/Xilinx/XRT" [Overview]: https://qiita.com/ikwzm/items/0d3a8adfe725cd17f932 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Overview) "@Qiita" [Build]: https://qiita.com/ikwzm/items/d8013ea91125a3fc46aa "Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Build)" @Qiita " [Installation]: https://qiita.com/ikwzm/items/6612eacc4a0d324a0a68 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Installation) "@Qiita" [Practice]: https://qiita.com/ikwzm/items/58cfea3f9d0f42840511 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Practice) "@Qiita" [Vitis Edition]: https://qiita.com/ikwzm/items/e70d8d0e44fe3784a708 "" Running XRT (Xilinx Runtime) on Debian GNU / Linux for Ultra96 / Ultra96-V2 (Vitis Edition) "@Qiita" ["Debian GNU / Linux (v2019.2 version) boot image for UltraZed / Ultra96 / Ultra96-V2" @Qiita]: https://qiita.com/ikwzm/items/92221c5ea6abbd5e991c "" UltraZed / Ultra96 / Ultra96- Debian GNU / Linux for V2 (v2019.2 version) Providing boot image "@Qiita" ["FPGA support situation in Linux Kernel 4.10" @Qiita]: https://qiita.com/ikwzm/items/2ff7d5429da8ace7c0bd "" FPGA support situation in Linux Kernel 4.10 "@Qiita" ["Introduction of Partial Reconfiguration of FPGA (Vivado Design Flow)" @Qiita]: https://qiita.com/ikwzm/items/1ffb695bc1b6c8679710 "Introduction of Partial Reconfiguration of FPGA (Vivado Design Flow)" @Qiita "

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